Background

Multiple-valued logic (MVL) circuits have advantage over binary circuits in dynamic power dissipation and area of interconnections because they can realize more data transmission over an interconnection wire. CNFETs are ideal to implement MVL circuits because the threshold voltages of CNFETs can be tuned by adjusting their diameters.

Problem Statement

In this project, I perform an in-depth literature review and compare existing adder cell designs in order to find the most optimal circuit topology for low-power and high-performance applications. The same operational conditions of supply voltage, input frequency, and output capacitance are applied to all circuits. Factors such as power consumption, delay, power-delay product, and transistor count are considered in the design evaluations.

Conclusion

In order to optimize the chip area, not only do we need to make the most effective use of the active silicon elements, but we also need to reduce the intra-chip connections and routings. MVL designs are superior to binary ones in this regard and allow more compact systems to be designed. Since reduction in the number of interconnects and switching will result in a reduction of dynamic power consumption, low- power CNFET-based MVL adders have the potential to make systems more power-efficient.