Introduction
Given a p-type Silicon substrate wafer, I fabricated and tested the n-channel MOSFETs. The project consisted of 10 fabricating labs and 1 testing lab.
Project Description
In Lab 1 and 2, I measured the sheet resistance using a four-point probe and extracted the theoretical doping of the wafer. I then grew field oxide for electrical isolation between active device regions.
In Lab 3, I measured the thickness of the field oxide using different methods such as color chart, Nanospec and Dektak instruments. Using lithography and wet etch, I defined MOSFET active areas.
lab 4
In Lab 4, I grew gate oxide by dry oxidation and deposit Polysilicon using Low-Pressure Chemical Vapor Deposition (LPCVD) method to obtain 500-Angstrom-thick oxide and 5000-Angstrom-thick Polysilicon. The gate oxide serves as an insulator while the Polysilicon will later be highly doped to serve as a metal node. Before growing oxide, I did pre-furnace clean in order to remove impurities, particulates, and native oxide on the wafer surface.
lab 5
In Lab 5, I used photolithography to define the Polysilicon gate pattern and align it to the active area pattern. Gate photolithography defines the channel length of the MOSFETs, which is the smallest dimension on the wafer.
lab 6
In Lab 6, I dry etched the Polysilicon that would define the gate electrode and wet etched the gate Silicon dioxide that would define the source/drain areas. Using reactive ion etch, I etched Polysilicon on front side of the wafer and stopped on gate oxide. After the etch, I proceeded to descum to remove deposited polymer from reactive ion etch. I then stripped the photoresist to completely remove the photoresist from the wafer surface before etching the gate silicon oxide. Finally, I wet etched the gate oxide down to the Source/Drain regions using Polysilicon as a hard mask. In both etching processes, I inspected the wafer to ensure the etch yields a desirable profile.
lab 7
In Lab 7, I formed doped source/drain and gate regions. I deposited a Phosphorus-doped Silicate Glass (PSG) on top of the wafer, etch PSG to leave phosphorus behind on the silicon surface, and drive oxide into the wafer so that phosphorus diffuses deeper into the silicon substrate's source/drain and gate regions.
lab 8
In Lab 8, I used lithography to define the contact hole openings for source/drain and gate levels, etched the drive-in oxide to form openings, and deposited Aluminum to make the contact.
lab 9
In Lab 9, I used lithography to define the Aluminum contact pads for source/ drain and gate and etched Aluminum between pad areas.
lab 10
In Lab 10, I removed the Polysilicon from the backside of the wafer, deposited Aluminum using DC magnetron sputtering, and thermally annealed the aluminum contacts.
before testing
final product
Check out my testing report